Tag Archives: pop

3D IC Packaging and 2.5D/3D IC Integration

PD30, Thursday, March 27, 2014, from 2:00 to 5:00 pm 2.5D/3D IC integration is taking the semiconductor industry by storm. It has been: (a) impacting chip suppliers, fab-less design houses, foundries, integrated device manufacturers, outsourced semiconductor assembly and test, substrates, electronic manufacturing service, original design manufacturers, original equipment manufacturers, material and equipment suppliers, universities, and research […]

Bob Willis with a few thoughts on PoP

Bob Willis shares a few of the issues involved with package-on-package (PoP) assembly in this short video. Issues include advantages of flux or paste, surface finish considerations, investment needed, and requirements for inspection. Bob will be teaching a half-day course on PoP at IPC APEX EXPO on April 8.