Strong and Varied Opinions Expected at IPC Microvia Virtual Summit

The upcoming IPC Microvia Virtual Summit (July 15-16) offers presentations from subject matter experts focused on determining the root causes for observed weak interface failures as well as mitigation techniques and test protocols.

IPC Events Connection (EC) editorial staff went behind the scenes to talk to IPC’s John Perry, director, printed board standards and technology, to find out how the challenge of weak microvias came to the attention of his committees.

EC: You are responsible for setting up meetings and leading committee members through numerous activities related to printed board fabrication and acceptance. Can you tell us how and when the issue of weak microvias came to the attention of IPC? Which committees were involved in the initial discussions?

JP: Our test coupon design, printed board performance and thermal stress testing task groups had already been working collectively, going back over 10 years, on new ways to thermally stress board samples to screen for latent via defects, but things really began to hit home several years ago when we were approached by a number of OEMs who were dealing with multiple instances of high-profile, expensive functional failures of product – product that had passed existing IPC and OEM testing and inspections and had featured stacked and/or staggered microvia structures.

EC: Is there a global awareness of this issue? How is that reflected in committee meetings?

JP: We’ve heard from OEMs in North America and Europe who have experienced microvia failures in deployed product that had passed traditional IPC-6010 performance specification evaluations, which included thermal stress testing such as IPC-TM-650 Method 2.6.8 and microsection inspection of legacy IPC-2221 A/B test coupons.  So, it has validated our goals of providing better and more modern test coupon designs and testing protocols.

EC: How are the committees currently addressing the possible solutions to the issue of testing? Is there a consensus on next steps? If not, how will that be addressed at the IPC Microvia Virtual Summit?

JP: We’ve had a collective IPC committee effort in place, including the 1-10c Test Coupon, D-32 Thermal Stress Methodology, D-33a IPC-6012, D-12 IPC-6013 and D-22 IPC-6018 groups, and have come up with a couple of integrated solutions:

First, through industry standard consensus, we’ve designed newer test coupons that can better represent the complex stacked and staggered microvia structures present in many board designs, through the IPC-2221B Appendix A.  This suite of test coupons has been developed through industry consensus and are available to anyone who wants to use them.

Second, we’ve developed the IPC-TM-650 Test Method 2.6.27B, which provides for thermal stressing of IPC-2221B Appendix A test coupons in a convection reflow environment with continuous electrical resistance measurements throughout the reflow profiles.  Our group of IPC committees feel that replicating the type of thermal reflow profiles that the actual production boards will be subjected to throughout the manufacturing process is a better way to thermally stress test coupon samples.  When you pair that up with the continuous monitoring of the percent change in resistance during reflow simulation, OEMs have told us that this procedure has helped to shelter them from numerous possible defect escapes, in comparison with other thermal stress procedures that have been used in the industry for many years.

EC: Which IPC standards reflect this issue? Are there new standards in development?

JP: We published the IPC-2221B printed board design standard with the Appendix A test coupon suite a number of years ago, and we make the Appendix A itself available for free download from our website, as we continually add and update coupons in that design suite.  Anyone can freely make use of these test coupon designs.

We also published Revision E to the IPC-6012, Qualification and Performance Specification for Rigid Printed Boards, earlier this year in March.  In that revision we’ve added a caution statement about the microvia-to-target land plating failure mode, and offered suggestions on performance-based acceptance testing using the IPC 2.6.27B test method and the IPC-2221B Appendix A “D” via integrity test coupon.

And later this year we will begin work on an Amendment to IPC-6012E that provides requirements for the usage of the IPC-2221B Appendix A test coupons in printed board production lot acceptance testing, giving OEMs the option to specify the usage of the more modern test coupons for lot acceptance.

EC: Is there a consensus on test protocols or can we expect opposing viewpoints on the best way to test for microvia reliability?

The test coupon designs provided by IPC-2221B Appendix A were developed through industry consensus and are freely available – anyone can make these test coupons if they desire.  And the test protocol called out in IPC-TM-650 Method 2.6.27B? Anybody can make a thermal oven that meets the profiles called out in that test method.  I’m not saying it is easy to build a system that can make the number of electrical resistance measurements required throughout the thermal profiles in that test method, but the test coupon designs and the test procedure are not proprietary – anyone can use them and make them if they desire.

The same cannot be said for some of the older thermal stress test protocols out there.  You’re going to hear strong and varying opinions on these different testing protocols within the IPC Microvia Virtual Summit, but hey, that’s okay, isn’t it?  In the long run, healthy, even contentious debate is a good thing for the industry, right?

For more information on the IPC Microvia Virtual Summit, July 15-16, visit www.ipc.org/Microvia-Summit.

 

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