Technology Spotlight: How Semi-Additive Processes Enable Finer Circuit Features

By Tara Dunn, president, Omni PCB

Can you imagine the benefits of routing with a 25-micron trace and space? Just to name a few; complex pin outs would require fewer layers and a decrease in costly lamination cycles, the overall size of the PCB could be dramatically reduced, or conversely, additional electronics could be fit into an existing footprint. What if the 25-micron technology could be integrated into a stack-up with traditional subtractive etch technology? To spark that imagination, a 10-layer PCB, pushing traditional design limits requiring stacked or staggered micro vias and three lamination cycles, could use 25 micron trace and space on tight pin out layers, while keeping other layers as designed resulting in a reduction in overall size and thickness, a reduction to 8 layers and reduction to only one lamination cycle.

Semi-additive technology enables the fabrication of 25-micron line and space and below and can be integrated with traditional PCB fabrication processes. This ultra-high-density packaging and interconnect solution can reduce size and weight by 90% over current state of the art processes within the US, is shown to have significant RF advantages over traditional subtractive-etch processing and is opening up design possibilities that were previously unavailable.

Mike Vinson, Averatek Corporation, will speak at IPC’s APEX EXPO 2020 technical conference about a semi-additive PCB fabrication process that is currently being licensed to North American based PCB fabricators. His presentation, “Transitioning to Very High-Density Interconnect From Subtractive to A-SAP™,” will cover how this process is different than our traditional subtractive etch processes, how those differences enable the manufacture of these fine feature sizes and how this technology can benefit next generation electronics.

As a sneak peek, rather than creating the circuitry from a traditional copper clad laminate and etching the copper that is not required, this semi-additive process starts with the bare substrate and adds copper to create the circuitry. Starting with a very thin electroless copper layer rather than copper foil enables these fine feature sizes. Once the circuit image is created, electrolytic copper finishes the circuit plating. Because the initial electroless copper is so much thinner than any of the foil options, the flash etching to remove the unnecessary copper does not noticeably impact the circuit pattern. This process results in traces with horizontal sidewalls rather than trapezoidal in shape, realizing benefits in both size and RF properties. Once the circuit pattern is created, the circuit layers follow most of the traditional PCB fabrication processes.

You can learn more at the IPC APEX EXPO technical session Tuesday, February 4 at 1:30-3:00 pm and discuss this technology with a panel of experts at the interACTION session Tuesday, February 4 at 3:30-5:00 pm. For more information, visit

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