3D Packaging and Fan-Out Wafer-Level Packaging (FOWLP)

By: John H Lau, ASM, john.lau@asmpt.com

Apple has been shipping their iPhone 7/7+ with their A10 application processor (AP) packaged by TSMC’s InFO (integrated fan-out) wafer-level packaging technology (or simply FOWLP) since September 2016. This is very significant, since Apple and TSMC are the “sheep leaders”. Once they used it, then many others will follow. Also, this means that FOWLP is not just only for packaging baseband, RF transceiver, PMIC (power management IC), audio codec, etc., it can also be used for packaging large (125mm2) SoCs (system-in-chips) and high-performance chips such as APs.

As a matter of fact, a long list of companies such as Apple, MetiaTek, HiSilicon, and Qualcomm are queuing for TSMC’s 10nm/7nm process technology and their fan-out packaging technology. Other companies such as Samsung are also working on fan-out technology for their and others’ APs.

STATSChipPAC has been shipping more than 2-billion of FOWLP. ASE will be in volume (20,000 wafers per month) production of FOWLP by the end of 2016 SPIL will start volume production early 2017. PowerTech will start their panel-level fan-out packaging in Q2 2017.

With the popularity of SiPs (system-in-packages), fan-out (which can handle multiple dies) will be used more because the fan-in WLCSP (wafer-level chip scale package) can only handle single die.

In general, fan-out technology eliminates the wafer bumping, fluxing, flip chip assembly, cleaning, underfill dispensing and curing, and package substrate. Eventually, it will lead to a lower cost and profile packaging technology.

Recent advances in 3D IC integration (Hynix/Samsung’s HBM for AMD/NVIDIA’s GPU and Micron’s HMC for Intel’s Knights Landing CPU), 2.5D IC Integration (TSV-less interconnects and interposers), embedded 3D hybrid integration (of VCSEL, driver, serializer, polymer waveguide, etc.), and 3D MEMS/IC integration have been making impacts on the semiconductor advanced packaging.

On Monday, February 13, 2017, from 2:00 to 5:00 pm, I will give a professional development course, “3D Packaging and Fan-Out Wafer-Level Packaging at IPC APEX EXPO to be held at the San Diego Conference Center. Course contents are shown below. Please join me.


  1. Introduction
  2. Fan-Out Wafer/Panel-Level Packaging(2) Fan-out Wafer/Panel-Level Packaging Formations
  3. (1) Patents Impacting the Semiconductor Packaging
  • Chip-first (die-down)
  • Chip-first (die-up)
  • Chip-last (RDL-first)
  • (3) RDL Fabrications
  • Polymer method
  • PCB/LDI method
  • Cu damascene method(5) TSMC InFO-PoP vs. Samsung ePoP(7) Notes on Dielectric and Epoxy Mold Compound(9) Wafer-Level System-in-Package (WLSiP)
  • (10) Package-Free LED (Embedded LED CSP)
  • (8) Semiconductor and Packaging for IoTs (SiP)
  • (6) Wafer vs. Panel Carriers
  • (4) TSMC InFO-WLP

(C) 3D IC Integration with TSVs

(1) Memory Chip Stacking – Samsung’s DDR4

(2) Hybrid Memory Cube (HMC) – Micron/Intel’s Knights Landing

(3) High Bandwidth Memory (HBM) – Hynix/AMD’s and Samsung/Nvidia’s GPU

(4) Chip stacking by TCNCF

(5) Samsung’s Widcon

(6) 3D IC/MEMS Integration

(7) Embedded 3D Hybrid Integration

(D) 2.5D IC Integration and TSV-Less Interposers

(1) TSMC/Xilinx’s CoWoS

(2) Xilinx/SPIL’s TSV-less SLIT

(3) SPIL/Xilinx’s TSV-less NTI

(4) Amkor’s TSV-less SLIM

(5) ASE’s TSV-less FOCoS

(6) MediaTek’s TSV-less RDLs by FOWLP

(7) Intel’s TSV-less EMIB

(8) ITRI’s TSV-less TSH

(9) Shinko’s TSV-less i-THOP

(10) Cisco/eSilicon’s TSV-less Organic Interposer

(11) Samsung’s TSV-less Organic Interposer

(E) Semiconductor Packaging New Trends

(F) Summary and Q&A








Post a Comment

Required fields are marked *


%d bloggers like this: