3D IC Integration and 3D IC Packaging

3D IC integration is taking the semiconductor industry by storm. It has been: (a) impacting chip suppliers, fab-less design houses, foundries, integrated device manufacturers, outsourced semiconductor assembly and test, substrates, electronic manufacturing service, original design manufacturers, original equipment manufacturers, material and equipment suppliers, universities, and research institutes; (b) attracting researchers and engineers from all over the world to go to conferences, lectures, workshops, panels, and forums to present their findings, exchange information, look for solutions, learn the latest technologies, and plan for their futures; and (c) pushing the industry to build standards, infrastructures, and ecosystems for 3D IC integration.

This is a perfect storm! People think that Moore’s law is going to roll off soon, and 3D IC integration can be the solution. In order to prepare for the future and get competitive edges, companies and research institutes have been investing heavily on both human and physical resources for 3D IC integration.

Meanwhile, 3D IC packaging such as stacking chips with wirebondings, package-on-package (PoP), chip-to-chip interconnects, embedded passives and actives, and fan-out embedded WLP have been used by mobile products, such as smartphones and tablets, and will be the main driver for materials consumption and new materials development for the wearable products like smartwatch.

On Monday, February 23, 2015, from 9:00 to 12:00 pm, I will give a professional development course (PD14) at IPC APEX EXPO to be held at the San Diego Conference Center. Course contents are shown below. Please join me.

1. 3D IC Packaging
(a) Stack Chips by Wire Bonding
(b) Package-on-Package (PoP)
(c) Chip-to-Chip Interconnect
(d) Fan-Out Embedded Wafer Level Package

2. TSV Technology
(a) Potential Applications of TSV
(b) Via Formation
(c) Dielectric Layer Deposition
(d) Barrier Layer and Seed Deposition
(e) Cu Plating
(f) Chemical-Mechanical Polishing

3. Micro Bumping, Assembly, and Reliability
(a) Fine-Pitch Cu-Pillar + Solder Cap Bumps
(b) Fine-Pitch Cu-Pillar + Solder Cap + Underfill
(c) Reliability data

4. 3D IC Integration
(a) Memory-Chip Stacking
(b) Wide I/O DRAM and Wide I/O 2
(c) Hybrid Memory Cube (HMC)
(d) HMC Examples: Intel, Fujitsu, Altera, Pico Computing, etc.
(d) High Bandwidth Memory (HBM)
(e) Wide I/O Memory (or Logic-on-Logic)
(f) Samsung’s Widcon

5. 2.5D IC Integration
(a) Design for Cost, Performance, Power, and Reliability
(b) Interposers
(c) Low-Cost Interposers
(d) Re-Distribution Layers; Polymer and Cu Damascene Methods
(e) Thin-Wafer Handling and Cu Revealing
(f) Conventional Integration Process Flow
(g) TI Stacked TSV-WCSP Integration Process Flow
(h) TSMC’s Integration Process Flow with Molding
(i) TSMC’s Integration Process Flow with Molding and heat sink
(j) ITRI’s Integration Process Flow with a Heat Spreader Wafer
(k) Next Generation of Package Substrates

6. Supply Chains and Ownerships for 2.5D/3D IC Integration

7. Thermal Management of 2.5D/3D IC Integration

8. 3D MEMS/IC Integration

9. 3D LED/IC Integration

10. 3D CIS/IC Integration

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