Designers of electronic products are always pushing to reduce size and weight while adding more functionality. That often puts them at the forefront of the evolution of high density chips and printed boards.
Copper pillar micro bump technology is one of the favored chip-to-package interconnection methods, gradually taking the place of conventional techniques that use wire bonding technology. Among several benefits that copper pillar technology offers, fine pitch scaling capability is one of the most effective ways to help achieve a small form factor package while accommodating higher I/O density.
Myung-June (MJ) Lee, principal engineer for package development for Altera Corp., noted that it is difficult to support bump-to-bump pitches less than 130 microns using solder bumps. But copper pillars make it possible to go down to spacings of 40 microns.
Lee will discuss Altera’s experiences with copper pillar packaging development at IPC APEX EXPO®, which runs from March 23-27, 2014 in Las Vegas. Lee plans to address key challenges on both reliability and package assembly processes, describing what he learned to do to deploy the technology, as well as what he learned not to do. Copper trace design on a substrate for robust micro-joint reliability, TCNCP (thermal compression with non-conductive paste) technology and substrate technology (structure and surface finish) are just a few of the topics he will address on Wednesday, March 26 as part of the technical conference session, “Assembly and Reliability of Bumped Components.”