Whether it’s called chip stacking, 3-D packaging or package on package (PoP), this system in package concept is extremely likely to be part of the future for many board and EMS companies over the next couple years. Major companies are ramping up programs, and system designers are seeking the benefits that come when chips are packaged vertically instead of horizontally.
At IPC APEX EXPO® in San Diego last month, Myung-June Lee of Altera Corp. said that advanced interconnects are letting companies map strategies that move at a faster pace than Moore’s Law. It take more than a year to go from one generation of silicon technology to the next, such as advancing from 40 to 28 nanometer line widths. Stacking lets designers put more computing power in less space in far less time.
With PoP, system engineers can shrink horizontal board space by building up. This concept is already seeing acceptance in cell phones, so the height increase can’t be too prohibitive. In many technical presentations and private interviews, I didn’t hear a soul say they’re betting against this technology.
Perhaps the key driver is that system designers want to leverage existing products that are becoming cheaper as volumes rise rather than waiting for the next generation of silicon to bring big advances with equally high price tags.
These system demands will be examined at the upcoming IPC Electronic System Technologies Conference (IPC ESTC), which will take place May 20–23 at the New Tropicana Hotel in Las Vegas. The conference will pull together OEMs, system and packaging suppliers and semiconductor suppliers. Whether you’re new to PoP or want to find out how the latest technical advances will impact your plans, Vegas is the place to be come May.