3D Packages are Ready to Pop

There are many names for the idea of packaging one die on top of another – stacked, 3D, package on package (PoP) are a few. These technologies have been around for decades, but it’s beginning to look like they’re going to start moving further into the mainstream.

Market researchers are predicting solid growth. TechSearch International has noted that the infrastructure is falling into place, and Yole Development is bullish about the role of 3D packaging in memories. Flash chips and other devices began employing through silicon vias in the last couple years, providing interconnections that make stacking simpler.

Many factors have kept PoP technology from making a broader impact over the past several years. Cost and reliability are at the core of it – it’s not cheap to create solder connections will hold up over the long term.

Now that it this packaging technology appears to be heading into the mainstream, it’s time for board fabricators, contract manufacturers and others to start looking more closely at the challenging requirements for stacked packages. If you’ve got an hour to spare on Feb. 22, you will want to sign up for an upcoming IPC Webinar, Interconnect Durability of Package on Package Assemblies.

This 10 -11 AM CST session will present an assessment of solder interconnect reliability of PoP assemblies produced by either pre-stacking or in-line stacking and reflow. Michael Osterman, director of the University of Maryland’s CALCE Operations, will examine the tradeoffs between these two methods. PoP may have taken a long time to develop, but it could well have a pretty quick uptake. It’s definitely time to start learning how PoP will impact this industry.

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