Activity in 3D packages increases

The idea of stacking one die atop another has been around for decades, but it finally seems to be catching on and moving into the mainstream. A couple recent linkups add some impetus to the takeoff and standards are already moving into place.

Stacked packaging, also called package on package, is now used primarily in memories. They’re stacked atop each other to increase density in applications like servers. But this month, there have been moves to make it easier to get the products built and assembled on boards.

Synopsys, Inc., a leading provider of chip design and verification software has teamed up with imec, a Belgian nanoelectronics research center. imec will use Synopsys finite-element tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias in stacked modules.

Stacking die boosts density and also brings some speed enhancements and reductions in power consumption. But it also brings new issues that can potentially affect its reliability and performance. Synopsys and imec say that their collaboration will speed commercialization by resolving these issues.

In another recent move, Camtek Ltd. said an unnamed Taiwanese chip house plans to use Camtek’s Falcon 800 metrology and inspection tools. Assuming it’s one of the major Taiwanese suppliers, it’s another sign that 3D is going mainstream.

If it does, inspectors will be able to get into the swing of things quickly. IPC has already added package on package technology in the new version of IPC-A-610E, Acceptability of Electronic Assemblies, publication expected in mid-April. That will help move the market to a wider range of customers.

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