Now Available: IPC-TM-650, Method, Dielectric Withstanding: Voltage (HiPot Method) – Thin Dielectric Layers for Printed Circuit Boards)

The dielectric withstanding voltage test (Hipot test) consists of the application of a voltage higher than the operating voltage for a specific time across the thickness of the test specimen’s dielectric layer. This is used to prove that a printed board can operate safely at its rated voltage and withstand momentary voltage spikes due to switching, surges, and other similar phenomena. Although this test is similar to a voltage breakdown test, it is not intended for this test to cause insulation breakdown. Rather, it serves to determine whether the test specimen’s layers have adequate withstanding voltage. This document is applicable to thin dielectric materials such as those defined by the IPC-4821 embedded capacitor material specification.

The test method can be downloaded for free in electronic .pdf format at the IPC-TM-650 Test Methods Manual website, located at


  1. Posted July 27, 2010 at 8:30 am | Permalink

    In what way is it different than IEC 60335 or is it a product specific standard for electrical safety testing and di-electric voltage test?

    Which test lab implements this method?

    • Kim Sterling
      Posted July 27, 2010 at 10:39 am | Permalink

      Hello – Thanks for asking.

      In general, test labs in our industry should be familiar with the IPC test method. Here is a list of test labs who are IPC members:

      As to the comparison of IPC-TM (November 2009) to IEC 60335, we are not sure, but the IPC TM A does pertain, very specifically, to the thin materials defined in the IPC-4821, Specification for Embedded Passive Device Capacitor Materials for Rigid and Multilayer Printed Boards. The only information that our tech department found on IEC 60335 is that they deal with the safety of “household and similar electrical appliances.”

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