PD30, Thursday, March 27, 2014, from 2:00 to 5:00 pm
2.5D/3D IC integration is taking the semiconductor industry by storm. It has been: (a) impacting chip suppliers, fab-less design houses, foundries, integrated device manufacturers, outsourced semiconductor assembly and test, substrates, electronic manufacturing service, original design manufacturers, original equipment manufacturers, material and equipment suppliers, universities, and research institutes; (b) attracting researchers and engineers from all over the world to go to conferences, lectures, workshops, panels, and forums to present their findings, exchange information, look for solutions, learn the latest technologies, and plan for their futures; and (c) pushing the industry to build standards, infrastructures, and ecosystems for 3D IC integration.
This is a perfect storm! People think that Moore’s law is going to roll off soon and 3D IC integration can be the solution. In order to prepare for the future and get competitive edges, companies and research institutes have been investing heavily on both human and physical resources for 3D IC integration.
Meantime, 3D IC packaging such as stacking chips with wirebondings, package-on-package (PoP), chip-to-chip interconnects, embedded passives and actives, and fan-out embedded WLP have been used by mobile products, such as smartphones and tablets, and will be the main driver for materials consumption and new materials development for the wearable products like smartwatch.
On Thursday, March 27, 2014, from 2:00 to 5:00 pm, I will give a professional development course (PD30) at IPC APEX EXPO. Abbreviated course contents are shown below. Please join me.
(2) 3D IC Packaging without TSVs
(3) CMOS Image Sensor with TSVs
(4) MEMS with TSVs
(5) TSV Technology
(6) Microbump Technology
(7) Thin-Wafer Handling Technology
(8) 3D IC Integration with TSVs
(9) 2.5D IC Integration with TSVs Design for Cost, Performance, Power, and Reliability
(10) Supply Chain and Ownerships for 2.5D/3D IC Integration