U.S. Appellate Court Says Disclosure of Conflict Minerals Violates Free Speech

Today, the U.S. Court of Appeals for the District of Columbia Circuit ruled that a section of the U.S. Securities and Exchange Commission’s (SEC’s) conflict minerals reporting rule violates the First Amendment. Senior Circuit Judge A. Raymond Randolph cited both the Dodd-Frank Wall Street reform law and the SEC rule, writing that they “violate the First Amendment to the extent the statute and rule require regulated entities to report…on their website that any of their products have not been found to be…DRC conflict free.”

But he rejected claims by the three groups that filed the lawsuit — the U.S. Chamber of Commerce, the Business Roundtable and the National Association of Manufacturers — that the SEC conducted a flawed rulemaking and failed to weigh the costs of new regulations.

Download the decision here.

The rule will now go back to a lower court to determine whether the wording in the SEC’s rule, or the Dodd-Frank reform law underpinning it, is to blame for the free speech violations.

Although the rule and law are in legal limbo, companies may still face supply chain inquiries regarding conflict minerals.  In November 2012, a number of large electronics original equipment manufacturers (OEMs) including Advanced Micro Devices, Inc., Dell, General Electric, Hewlett-Packard, Intel Corporation, KEMET Electronics Corp, Microsoft Corporation and Motorola Solutions signed a statement that they would, “continue to work together to eliminate the link between violence and human rights abuses and the mineral trade in the Democratic Republic of the Congo (DRC) and surrounding countries regardless of the lawsuit.”

IPC will continue to monitor analysis of the decision and pass on additional information as it becomes available.


SEC Updates Conflict Minerals FAQ

GoldOn April 7, the U.S. Securities and Exchange Commission (SEC) updated its Dodd-Frank Wall Street Reform and Consumer Protection Act Frequently Asked Questions (FAQ) webpage with an additional nine questions pertaining to conflict minerals.

The updated document provides more information on:

  • the independent private sector audit (IPSA),
  • certain aspects of the IPSA trigger,
  • whether Reasonable Country of Origin Inquiry (RCOI) activities should be described in the Conflict Minerals Report (CMR),
  • the extent of the description of due diligence measures that is required for the CMR; and
  • the applicability of the “DRC Conflict Undeterminable” category.

Read complete FAQ.

To address the industry’s growing need for information, IPC has developed a number of tools to help companies understand the conflict minerals regulation and develop an effective conflict minerals program.

IPC’s Conflict Minerals Due Diligence Guidecovers information from who to include on a company’s conflict minerals team to what to include in a company policy statement. The guide also lays out steps for identifying and prioritizing suppliers. Due to the complexity of the electronics supply chain, it is imperative to identify key suppliers in order for them to be thoroughly vetted for conflict minerals information. This guide includes vital information on ensuring due diligence compliance is met as required by the SEC regulation.

The recently released IPC-1755, Conflict Minerals Data Exchange Standard helps suppliers and their customers effectively facilitate conflict minerals data exchange along the entire global supply chain. The standard includes easy-to-understand terms and definitions, descriptions of declaration classes, data requirements for a conflict minerals declaration and verification guidance.

For additional information on conflict minerals resources and IPC’s advocacy efforts, visit www.ipc.org/conflict-minerals.


IPC Comments on RoHS2 Substance Revisions

TBBPAToday, IPC submitted comments on the European Union (EU) Stakeholder Consultation, “Study for the review of the list of restricted substances under RoHS2 – Analysis of impact from a possible restriction of several new substances under RoHS2.”

Within the comments, IPC highlighted its disagreement with the Umweltbundesamt (UBA) identification and ranking of Tetrabromobisphenol-A (TBBPA) as a second highest priority substance for potential restriction under the Restriction of Hazardous Substances (RoHS) Directive. According to an EU Risk Assessment, TBBPA has been found to be safe for human health and the environment and should not be considered for further assessment under the RoHS Directive.

During the RoHS revisions process, IPC successfully lobbied for the revised Directive to be scientifically based. As a result, the EU did not implement additional substance restrictions under the revised RoHS Directive, but the Commission was required to complete a review of Annex II by July 2014. Although TBBPA, will not be proposed for restriction in 2014, it could be considered for restriction as early as 2016.

IPC will remain engaged in the review process and will continue to advocate for science-based regulations.

See previous blog item, Final Recommendations for Additional Substances to be Restricted under RoHS Published for more information on IPC’s comments on the EU’s draft methodology.

Nvidia Jumps on Package-on-Package Bandwagon

Package-on-package got another endorsement last week when Nvidia said it would use 3-D packaging on some forthcoming Pascal graphics processors to make more memory available with minimal delays. The move comes as more industries are adopting the company’s parallel processing chips.

Nvidia President and CEO Jen-Hsun Huang made 3-D packaging one of the first highlighted technologies at the company’s annual GPU (graphics processing unit) Technology Conference. GPUs are now limited by power and pin count, he explained. A key factor for the pin limitation is that parallel processors require lots of bandwidth and wide data paths to large memory blocks.

Stacking memory chips will let the company provide lots of memory that can be accessed quickly. Huang noted that 3-D stacking will let the company “take bandwidth to new levels over the next two years.” Memory interfaces are migrating from hundreds of bits to thousands of bits, he added.

Memory chips will utilize through silicon vias. They will be stacked on wafers, so the distance from processors to memories will be minimal. Nvidia’s move marks a major step forward for package-on-package technologies. The company’s processors are no longer limited to video gaming and graphics. Military and automotive applications are just a couple of the industries that are moving to its GPUs. When a company that plays in both high-volume and high-reliability markets adopts a technology, it’s a good sign that technology is moving into the mainstream.


Do You Know which Stencil Works Best?

Photo Stencil  Staff Present “Print Performance Studies Comparing Electroform and Laser-cut Stencils” at IPC APEX EXPO  

S04-Printing I, March 25 from 1:30-3:30 PM

blogPhoto Stencil, LLC staff  will present, “Print Performance Studies Comparing Electroform and Laser-cut Stencils,” at IPC APEX EXPO on Tuesday, March 25th from 1:30–3:30 pm at Technical Session S04-Printing I. Presented by Rachel Miller-Short and written in collaboration with William E. Coleman Ph.D., of Photo Stencil and Joseph Perault of Parmi, the presentation fully evaluates various stencil types available in the industry today to determine which provide the best paste release results for small apertures while providing enough solder paste volume for normal-sized SMT components. The study includes a comparison of laser-cut electroformed blank foils as an alternative to normal electroformed stencils, and, in addition to electroformed stencil variations, evaluated various coatings and post processed stencils.

“As components get smaller, it is difficult to print solder paste to satisfy the requirements of both very small components, such as .4 and .3mm pitch CSPs, as well as normal SMT components,” explained Rachel Short, VP sales and marketing, Photo Stencil. “The large components require more solder paste volume for sufficient solder fillets after reflow; however, if the stencil normally used to print solder paste for SMT components is used for the small components, the apertures are so small that poor paste release may be encountered. The area ratio plays a large part in this dilemma. Our study details the performance of 12 stencils in 5 different categories.”

In addition, Dr. Coleman will present the poster “Two Print Stencil Systems” on Wednesday, March 26, at 3:30 pm in the South Pacific F. The poster demonstrates two print stencil systems for:

  • Printing solder paste for SMT and through-hole intrusive reflow.
  • Printing solder paste for SMT and RF shields.
  • Printing solder paste and glue.
  • Printing solder paste and flux for SMT/flip chip assembly.
  • Printing solder paste on two different PCB levels.

For more information, visit www.photostencil.com/events.php.

Satisfying the Hunger for Knowledge

foodWhen people decide which trade show they want to attend, they often face a choice that’s a bit like picking a restaurant. They can go to a buffet-like conference where there are many different presentations that don’t have a lot of depth, or go to a specialized show that offers truly good information in a focused area.

IPC APEX EXPO is one of the rare conference and exhibitions that offers a large menu of topics with presentations that have plenty of meat. For example, Lars Bruno of Ericsson and MTEK’s Tord Johnson will team up to discuss quality assurance issues for solder paste printing on double-sided boards that have as many as 35,000 pads with a mixture of power modules and small components.

A presentation by a team from Intel and Arizona State University will describe an automated solder ball height detection scheme that uses stereo vision. They say that’s far easier to implement than existing techniques like laser profiling. This inspection technique can significantly improve manufacturing yields.

Humair Mandavia of Zuken USA tackles the challenges of implementing embedded components, taking a holistic view that runs from concept to manufacturing. He’ll explain tradeoffs that must be made during the conceptual stages through placing the parts. Mandavia will also explain ways to conduct checks to make sure that designs can be manufactured.

Those are just a few of the many technical presentations that will occur at the show, which runs from March 23-27. It really doesn’t matter what you’re hungry for when you go to Las Vegas for APEX IPC EXPO. You’re bound to come home satiated.

Joint Team Trims Standard Development Cycle

Getting multiple groups to work together often extends the time it takes to finish a project. But when IPC and JEDEC teamed up to create a standard for grid array package testing, they shortened the typical standard development cycle.

IPC/JEDEC-9706, Mechanical Shock In-situ Electrical Metrology Test Guidelines for FCBGA SMT Component Solder Crack and Pad Crater/Trace Crack Detection, was completed in 12 months. It’s one of many IPC standards that are being completed in shorter timeframes.

It didn’t hurt that the point people for the IPC and JEDEC committees were friends who worked in the same Intel facility. Ramgopal Uppalapati and Ife Hsu, who worked with the respective IPC and JEDEC committees, helped to develop the metrology technique. When questions arose from the committee members who turned the Intel-developed technology into a universal tool, they typically had the right answers.

Both groups worked on the technology simultaneously. The chairmen then pulled together the input from each committee. They say the simultaneous work prevented the zigs and zags that can occur when different groups take dissimilar paths.

The quick turnaround highlights IPC efforts to shorten development cycles. More work is being done remotely as volunteers leverage Web-based conferencing technologies. Uppalapati noted that IPC managers are very open to changes, which helps creative committee chairmen get the most from their committee members.

3D IC Packaging and 2.5D/3D IC Integration

PD30, Thursday, March 27, 2014, from 2:00 to 5:00 pm

2.5D/3D IC integration is taking the semiconductor industry by storm. It has been: (a) impacting chip suppliers, fab-less design houses, foundries, integrated device manufacturers, outsourced semiconductor assembly and test, substrates, electronic manufacturing service, original design manufacturers, original equipment manufacturers, material and equipment suppliers, universities, and research institutes; (b) attracting researchers and engineers from all over the world to go to conferences, lectures, workshops, panels, and forums to present their findings, exchange information, look for solutions, learn the latest technologies, and plan for their futures; and (c) pushing the industry to build standards, infrastructures, and ecosystems for 3D IC integration.

This is a perfect storm! People think that Moore’s law is going to roll off soon and 3D IC integration can be the solution. In order to prepare for the future and get competitive edges, companies and research institutes have been investing heavily on both human and physical resources for 3D IC integration.

Meantime, 3D IC packaging such as stacking chips with wirebondings, package-on-package (PoP), chip-to-chip interconnects, embedded passives and actives, and fan-out embedded WLP have been used by mobile products, such as smartphones and tablets, and will be the main driver for materials consumption and new materials development for the wearable products like smartwatch.

On Thursday, March 27, 2014, from 2:00 to 5:00 pm, I will give a professional development course (PD30) at IPC APEX EXPO. Abbreviated course contents are shown below. Please join me.

(1)   Introduction

(2)   3D IC Packaging without TSVs

(3)   CMOS Image Sensor with TSVs

(4)   MEMS with TSVs

(5)   TSV Technology

(6)   Microbump Technology

(7)   Thin-Wafer Handling Technology

(8)   3D IC Integration with TSVs

(9)   2.5D IC Integration with TSVs Design for Cost, Performance, Power, and Reliability

(10) Supply Chain and Ownerships for 2.5D/3D IC Integration

(11) Summary

(12)  Q&A

EU Proposes Voluntary Conflict Minerals Scheme

The European Union (EU) Commission’s Trade Directorate has proposed a voluntary self-certification scheme that would set up a “responsible importer” scheme for firms exercising due diligence over commodity supply chain for conflict gold and the “Three Ts” – tin, tungsten, and tantalum and their mineral ores. The voluntary self-certification scheme would require companies to exercise due diligence to demonstrate that their products’ mineral components did not finance human rights abuses, and would offer incentives ranging from EU public procurement contracts to funding possibilities for small and medium-sized enterprises (SMEs).

The proposed scheme will only apply to companies placing raw materials on the market – such as Europe’s 20 or so smelters – and not importers of products such as mobile phones, which may already have had the materials installed. Under the EU proposal, member states would have to nominate competent authorities to receive information and perform checks and audits (within the scheme) under the five steps of the process laid out in the Organisation for Economic Cooperation and Development (OECD) Due Diligence Guidance.

In proposing this voluntary scheme, the EU appears to have listened seriously to IPC and other industry players who have highlighted the difficulties experienced by companies attempting to comply with the 2010 U.S. Dodd-Frank Act, which obliges U.S. Stock-Exchange-listed firms to disclose minerals sourced from the DRC.

The EU’s Trade Directorate, which prepared the new regulation, sees it as a complementary law to the U.S. legislation that would concentrate on “upstream” actors and avoid imposing an extra burden on small European businesses. To increase public accountability of smelters and refiners, enhance supply chain transparency and facilitate responsible mineral sourcing, the EU plans to publish an annual list of EU and global “responsible smelters and refiners.”

The European Parliament, whose development committee passed a non-voluntary proposal on 19 February, could try to add more strict provisions to the proposal when they take it up in September. IPC and other interested parties will need to continue to stay engaged and support cost-effective measures.

IPC is actively engaged in advocating on behalf of our members and has met with EU Commission officials to urge them to proceed cautiously before implementing conflict minerals legislation especially in light of the negative, unintended effects of Dodd-Frank. In October, Signe Ratso of the EU Commission spoke at a conference hosted by IPC in Brussels. IPC members can view her presentation here.

IPC will remain actively engaged in the conflict minerals issue and will continue its advocacy efforts to promote conflict minerals legislation that avoids actions to unduly burdens manufacturing and commerce industries or cause unnecessary disruptions of the minerals trade. For more information about IPC’s advocacy and position on conflict minerals, visit IPC’s Conflict Minerals webpage.

Fundamental Considerations to EMC and High Speed Signal Behavior on PCBs

Following Albert Einstein’s model of making things as simple as possible, but not simpler, you too, can become an EMC-competent board designer by understanding what happens, rather than merely learning rules.

On Monday, March 24, 2014, from 2:00 pm to 5:00 pm, I, along with course attendees will examine sources of RF; electric and magnetic dipole antenna structures; and near-field arrangement that generate common and differential mode currents and create crosstalk and far-field radiation. Using 3-D field simulation, I will demonstrate design techniques for trapping RF generated by various applications.

In addition, my professional development course (PD26) at IPC APEX EXPO, “Becoming an EMC-competent Board Designer by Understanding What Happens Rather than Learning Rules,” will detail:
• Design rules and samples of EMS and high-speed PCB design
• Influence of connector placement on external noise
• Role of line and power structures in EM-field and high-speed signal propagation
• Current density distributions of different signal structures (single-ended and differential lines) to reconfirm proposed design structures
• Effects of slotted ground planes under signal traces and high-speed signal propagation switching between reference planes as demonstrated by 3-D field simulation with signal energy flow; and recommendations for optimal signal path and reference plans arrangement
• The influence of 90 trace inflections and non-matching differential trace length for high-speed signals as demonstrated by 3-D EM field simulation with signal integrity distortion

Learn to understand the impact of EMC on PCBs beyond the rules by joining me on Monday, March 24.


Get every new post delivered to your Inbox.

Join 180 other followers